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hy64ld16322m series 1 revision 1.6 march. 2002 this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described. no pate nt licenses are implied. document title document title 2 2 m x 16 bit low low power 1t/1c m x 16 bit low low power 1t/1c pseudo sram pseudo sram revision history revision history revision no. revision no. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 history history initial revised - change pin connection - improve toe from 45ns to 30ns - correct state diagram revised - correct package dimension - change absolute maximum ratings revised - dc electrical characteristics (i sb1 ,i dpd ,i cc1 ) - state diagram - power up sequence - deep power down sequence - read/write cycle note - release standby current from 100 m a to 120 m a revised - dc electrical characteristics (icc1: 3ma - > 5ma ) - power up sequence revised - improve icc2 30ma to 20ma - improve ambient temperature c/e to e/i ( 0 c ~85 c/ - 25 c ~85 c ? - 25 c ~85 c/ - 40 c ~85 c) - improve maximum absolute ratings ( vdd : - 0.3 v to 3.3v ? - 0.3 v to 3.6v) - improve toe 30ns to 20ns revised - pin description - power up & deep power down exit sequence draft date draft date jan. 04. ? 01 jul. 03. ? 01 jul.18. ? 01 oct. 06. ? 01 nov. 07. ? 01 feb. 27. ? 02 m ar . 11. ? 02 remark remark preliminary preliminary preliminary preliminary preliminary preliminary final
hy64ld16322m series 2 revision 1.6 march. 2002 this document is a general product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described. no pate nt licenses are implied. 2 2 m x 16 bit low low power 1t/1c m x 16 bit low low power 1t/1c sram sram description the hy64ld16322m is a 32mbit 1t/1c sram featured by high - speed operation and super low power consumption. the hy64ld16322m adopts one transistor memory cell and is organized as 2,097,152 words by 16bits. the hy64ld16322m operates in the extended range of temperature and supports a wide operating voltage range. the hy64ld16322m also supports the deep power down mode for a super low standby current. the hy64ld16322m delivers the high - density low power sram capability to the high - speed low power system. ? cmos process technology ? 2 m x 16 bit organization ? ttl compatible and tri - state outputs ? deep power down : memory cell data hold invalid ? standard pin configuration : 48 - f bga ? data mask function by /lb, /ub product family features note 1. tcs - /ub,/lb=high : chip deselect. product no. voltage [v] speed trc[ns] temp. [ c] ( i sb1 ,max) ( i dpd ,max) ( i cc2 ,max) power dissipation mode hy64ld16322m - df 85 i 2.3~2.7 85 - 40~85 1 2 0 m a 2 m a 2 0 ma 1 cs with /ub,/lb:tcs 1 hy64ld16322m - df 85 e 2.3 ~ 2.7 85 - 25~85 1 2 0 m a 2 m a 2 0 ma 1 cs with /ub,/lb:tcs 1 pin description pin name pin function pin name pin function / cs1 chip select io1~io8 lower data inputs/outputs / we write enable a0~a20 address inputs / oe output enable vdd power(2.3v~2.7v) / lb lower byte(io1~io8) vss ground / ub upper byte(io9~io16) cs2 deep power down dnu do not use io9~io16 upper data inputs/outputs pin connection (top view) block diagram add input buffer pre decoder column decoder block decoder row decoder sense amp write driver data i/o buffer memory array 2,048k x 16 control logic a0 a20 io1 io8 io9 io16 / cs1 cs2 / oe / lb / ub / we / lb / oe a0 a1 a2 cs2 io9 / ub a3 a4 / cs1 io1 io10 io11 a5 a6 io2 io3 vss io12 a17 a7 io4 vdd vdd io13 dnu a16 io5 vss io15 io14 a14 a15 io6 io7 io16 a19 a12 a13 / we io8 a18 a8 a9 a10 a11 a20
hy64ld16322m series 3 revision 1.6 march. 2002 note 1. stresses greater than those listed under absolute maximum rat ings may cause permanent damage to the device. this is stress rating only and the functio nal operation of the device under these or any other conditions above those indicated in the operation of t his specification is not implied. exposure to the absolute maximum rating conditions for extended period ma y affect reliability. truth table power standby / cs1 h cs2 h / we x / oe x / lb x / ub x mode deselected i/o1~i/o8 high - z i/o9~i/o16 high - z i/o pin x x l l l l l l l l l l h h h h h h h h h h x x l h h l h h l h h x x x l h x l h x l h x h l l l h h h l l l x h h h h l l l l l l deselected deselected write read output disabled write read output disabled write read output disabled high - z high - z high - z high - z d in high - z d out high - z high - z high - z d in high - z d out high - z d in d out high - z high - z high - z d in d out high - z deep power down standby active active active active active active active active active note 1. h=v ih , l=v il , x=don ? t care(v il or v ih ) 2. /ub, /lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when /lb is low, data is written or read to the lower byte, i/o1 - i/o8. when /ub is low, data is written or read to the upper byte, i/o9 - i/o16. ordering information part number speed package hy64ld16322m - e 85 f bga hy64ld16322m - i 85 f bga power ll - part ll - part temperature e 1 i 2 note 1. e : extended temp. ( - 25 c ~ 85 c ) 2. i : industrial temp. ( - 40 c ~ 85 c ) absolute maximum ratings 1 symbol parameter rating remark v in ,v out input/output voltage - 0. 3 to v dd+0.3 unit v vdd power supply - 0. 3 to 3.6 v t a a mbient temperature - 25 to 85 hy64 l d16 322 m - d f85 e c t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 ? 10 c ? sec - 40 to 85 hy64 l d16 322 m - d f85 i c
hy64ld16322m series 4 revision 1.6 march. 2002 note 1. vil= - 1.5v for pulse width less than 10ns undershoot is sampled, not 100% tested. recommended dc operating condition symbol parameter min. vdd supply voltage 2.3 unit v typ. 2.5 max. 2.7 v ss ground 0 v - 0 v ih input high voltage 2. 0 v - v dd +0.3 v il input low voltage - 0.3 1 v - 0.6 dc electrical characteristics vdd=2.3~2.7v, t a = - 25 c to 85 c(e) / - 40 c to 85 c(i) sym. parameter min. i li input leakage current - 1 unit m a typ. - max. 1 test condition v ss v in v dd i lo output leakage current - 1 m a - 1 v ss v out vdd, /cs1=v ih , cs2=v ih , /oe=v ih or /we=v il i cc operating power supply current - m a - 3 /cs1=v il , cs2=v ih , v in =v ih or v il , i i/o =0ma i cc1 average operating current - m a - 2 0 /cs1=v il , cs2=v ih , v in =v ih or v il , cycle time=min. 100% duty, i i/o =0ma - m a - 5 /cs1 0.2v, cs2 3 v dd - 0.2v, v in 0.2v or v in 3 v dd - 0.2v, cycle time=1 m s . 100% duty, i i/o =0ma i sb ttl standby current - m a - 0.5 /cs1,cs2=v ih or /ub,/lb= v ih i sb1 standby current(cmos input) - m a - 1 2 0 /cs1, cs2 3 v dd - 0.2v or /ub,/lb 3 v dd - 0.2v v ol output low voltage - v - 0.4 i ol = 0.5 ma v oh output high voltage 2. 0 v - - i oh = - 0.5 ma i cc2 i dpd deep power down current - m a - 2 cs2 v ss+ 0.2v capacitance ( temp = 25 c, f=1.0mhz) symbol parameter c in input capacitance(add, /cs1, cs2, /we, /oe , / ub, /lb ) unit pf max. 8 condition v in =0v c out output capacitance(i/o) pf 10 v i/o =0v note : these parameters are sampled and not 100% tested
hy64ld16322m series 5 revision 1.6 march. 2002 ac test conditions t a = - 25 c to 85 c(e) / - 40 c to 85 c(i), unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rising and fall time 5ns input and output timing reference level 1. 1 v output load s ee below ac test loads note 1. including jig and scope capacitance. ac characteristics vdd=2.3v~2.7v, t a = - 25 c to 85 c(e) / - 40 c to 85 c(i), unless otherwise specified # parameter min. 1 read cycle time 85 unit ns max. - symbol trc read cycle 2 address access time - ns 85 taa 3 chip select access time - ns 85 tacs 4 output enable to output valid - ns 2 0 toe 5 /lb, /ub access time - ns 85 tba 6 chip select to output in low z 10 ns - tclz 7 output enable to output in low z 5 ns - tolz 8 /lb, /ub enable to output in low z 10 ns - tblz 9 chip d i sable to output in high z 0 ns 3 0 tchz 10 out disable to output in high z 0 ns 3 0 tohz 11 /lb, /ub disable to output in high z 0 ns 3 0 tbhz 12 output hold from address change 10 ns - toh 13 write cycle time 85 ns - twc write cycle 14 chip selection to end of write 70 ns - tcw 15 address valid to end of write 70 ns - taw 16 /lb, /ub valid to end of write 70 ns - tbw 17 address set - up time 0 ns - tas 18 write pulse width 60 ns - twp 19 write recovery time 0 ns - twr 20 write to output in high z 0 ns 3 0 twhz 21 data to write time overlap 30 ns - tdw 22 data hold from write time 0 ns - tdh 23 output active from end of write 5 ns - tow - 85 c l 1 =30 pf d out r l =50 ohm v l =1.1 v z 0 =50 ohm
hy64ld16322m series 6 revision 1.6 march. 2002 standby mode characteristics mode memory cell data standby current [ m a] wait time [ m s] standby valid 1 2 0 0 deep power down invalid 2 200 state diagram 1. s upply power. 2. maintain stable power for longer than 200 m s. power - up sequence 1. keep cs2 low state. deep power down mode is maintained w hile cs2 i s low state. deep power down entry sequence 1. keep cs2 high state. 2. maintain stable power for longer than 200 m s. deep power down exit sequence power on power on power on wait 200 m s wait 200 wait 200 m m s s active active active standby mode standby standby mode mode deep power down mode deep power deep power down mode down mode / cs1=v il , cs2=v ih , /ub&/lb 1 v ih cs2=v il cs2=v il power - up sequence cs2=v ih , /cs1=v ih or /ub,/lb = v ih deep power down exit sequence deep power down entry sequence cs2=v ih
hy64ld16322m series 7 revision 1.6 march. 2002 notes : 1. read cycle occurs whenever a high on the /we and /oe is low, while /ub and/or /lb and /cs1 and cs2 are in active status. 2. /oe = v il 3. tchz, tbhz and tohz are defined as the time at which the outp uts achieve the high impedance state and tolz,tblz and tclz are defined as the time at which the outputs achieve the low impedance state. these are not referenced to output voltage levels. 4. /cs1 in high for the standby, low for active. /ub and /lb in high for the standby, low for active. timing diagram read cycle 1 ( note 1, 4 ) add / cs1 cs2 / ub, /lb / oe data out high - z vih trc taa tacs tba toe tolz (3) tblz (3) tclz (3) toh tchz (3) tbhz (3) tohz (3) data valid read cycle 2 ( note 1, 2, 4 )( cs2=vih ) add data out data valid trc previous data toh taa toh read cycle 3 ( note 1, 2, 4 )( cs2=vih ) / cs1 / ub, /lb data out data valid high - z tclz (3) tacs tchz (3)
hy64ld16322m series 8 revision 1.6 march. 2002 notes : 1. a write occurs during the overlap of low /cs1, low /we and l ow /ub and/or /lb. 2. twr is measured from the earlier of /cs1, /lb, /ub, or /we go ing high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be ap plied. 4. if the /cs1, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low (/oe=v il ) 6. q(data out) is the invalid data. 7. q(data out) is the read data of the next address. 8. twhz is defined as the time at which the outputs achieve the high impedance state. it is not referenced to output voltage levels. 9. /cs1 in high for the standby, low for active. /ub and /lb in high for the standby, low for active. 10. do not input data to the i/o pins while they are in the outp ut state. write cycle 1 ( note 1, 4, 5, 9, 10 ) ( /we controlled ) add / cs1 cs2 / ub, /lb / we data out d ata in vih twc tcw tbw twp twr (2) data valid taw tas high - z tdw tdh twhz (3,8) tow (6) (7) write cycle 2 ( note 1, 4, 5, 9, 10 ) ( /cs1 controlled ) add / cs1 cs2 / ub, /lb / we data out d ata in vih twc tcw tbw twp twr (2) data valid taw high - z tdw tdh high - z tas
hy64ld16322m series 9 revision 1.6 march. 2002 avoid timing / we / cs1 add < trc 3 10 us abnormal timing / we / cs1 add 3 trc 3 10 us avoidable timing(1) hynix 1t/1c sram has a timing which is not supported at read ope ration. if your system has multiple invalid address signal shorter than trc during over 10us at read operation which showed in abnormal timing, hynix 1t/1c sram needs a normal read timing at least dur ing 10us which showed in avoidable timing(1) or toggle the /cs1 to high( 3 trc) one time at least which showed in avoidable timing(2) / we / cs1 add 3 10 us 3 trc avoidable timing(2) < trc
hy64ld16322m series 10 revision 1.6 march. 2002 note. 1. dimensioning and tolerancing per asme y14.5m - 1994. 2. all dimensions are millimeters. 3. dimension ? d ? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension. package dimension note. 1. dimensioning and tolerancing per asme y14.5m - 1994. 2. all dimensions are millimeters. 3. dimension ? d ? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension. 48 ball fine pitch ball grid array package(f) unit : mm a a b1 b1 b b c1 c1 c c d d e e e1 e1 e2 e2 r r symbol symbol - - - - 6.90 6.90 - - 7.90 7.90 0.30 0.30 - - - - 0.20 0.20 - - min. min. 0.75 0.75 3.75 3.75 7.00 7.00 5.25 5.25 8.00 8.00 0.35 0.35 1.00 1.00 0.75 0.75 0.25 0.25 - - typ. typ. - - - - 7.10 7.10 - - 8.10 8.10 0.40 0.40 1.10 1.10 - - 0.30 0.30 0.08 0.08 max. max. b b c c top view top view a1 corner a1 corner index area index area e e e2 e2 side view side view c c a a 5 5 r r d(diameter) d(diameter) 3 3 e1 e1 seating plane seating plane 4 4 a a b1 b1 c1 c1 bottom view bottom view a a b b c c d d e e f f g g h h 6 6 5 5 4 4 3 3 2 2 1 1 a a c/2 c/2 b/2 b/2 a1 index a1 index mark mark
hy64ld16322m series 11 revision 1.6 march. 2002 marking information index ? hyld16322m : part name hy : hynix l : power supply : 2.5v(2.3v~2.7v) d : tech. + classification : 1t+1c 16 : bit organization : x16 32 : density : 32m 2 : mode : 1cs with /ub,/lb;tcs m : version : 1 st generation ? c : power consumption : d ? low low power ? ss : speed : 85 ? 85ns ? t : temperature : e ? extended( - 25 ~ 85 c ) i ? industrial( - 40 ~ 85 c ) ? yy : year (ex : 01 = year 2001, 02= year 2002) ? ww : work week ( ex : 12 = work week 12 ) ? p : process code ? xxxxx : lot no. ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item package marking example fbga h y l d 1 6 3 2 2 m c s s t y y w w p x x x x x k o r

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